One type of prior non-volatile semiconductor memory is the flash electrically erasable programmable read-only memory ("flash EEPROM"). The flash EEPROM can be programmed by a user, and once programmed, the flash EEPROM retains its data until erased. After erasure, the flash EEPROM may be programmed with new code or data.
Flash memories differ from conventional electrically erasable programmable read only memory ("EEPROMs") with respect to erasure. Conventional EEPROMS typically use a select transistor for individual byte erase control. Flash memories, on the other hand, typically achieve much higher density with single transistor cells. During one prior art erase modes for a flash memory, a high voltage is supplied to the sources of every memory cell in a memory array simultaneously. This results in a full array erasure.
For one prior flash EEPROM, a logical "one" means that few if any electrons are stored on a floating gate associated with a bit cell. A logical "zero" means that many electrons are stored on the floating gate associated with the bit cell. Erasure of that prior flash memory causes a logical one to be stored in each bit cell. Each single bit cell of that flash memory cannot be overwritten from a logical zero to a logical one without a prior erasure. Each single bit cell of that flash memory can, however, be overwritten from a logical one to a logical zero, given that this entails simply adding electrons to a floating gate that contains the intrinsic number of electrons associated with the erased state.
One prior flash EEPROM is the 28F256 complementary metal oxide semiconductor ("CMOS") flash memory sold by Intel Corporation, which is a 256 kilobit flash EEPROM. The 28F256 flash memory includes a common register to manage electrical erasure and reprogramming. Commands are written to the command register from a controlling microprocessor using standard microprocessor writing timings. The command register contents serve as input to an internal state machine that controls erase and programming circuitry.
The controlling microprocessor controls the erasure and programming of the flash memory. A prior Quick-Erase.TM. algorithm of Intel Corporation can be used by the microprocessor to erase the flash memory. The prior Quick-Erase.TM. algorithm requires that all bits first be programmed to their charged state, which is data equal to 00 (hexadecimal). Erasure then proceeds by pulling the sources of the transistors in the array up to the Vpp level for a period of 10 milliseconds. After each erase operation, byte verification is performed. The prior Quick-Erase.TM. algorithm allows up to 3000 erase operations prior to recognizing erasure failure. Proper device operation requires that the erasure procedure be strictly followed.
The prior Quick-Pulse Programming.TM. algorithm of Intel Corporation can be used by the microprocessor to then program the flash memory. The Quick-Pulse Programming.TM. algorithm requires that a programming pulse of a specific duration and voltage level be applied to the drain and gate of the selected transistors in the array. For example, for certain prior Intel flash memories a programming pulse of 10 microseconds has been suggested while Vpp is held at 12.75. After the programming pulse is applied, the user must verify whether the memory cell addressed is properly programmed. If not properly programmed, a programming pulse may be reapplied a number of times before a programming error is recognized. Intel's Quick-Pulse Programming.TM. algorithm allows up to 25 programming operations per byte. Proper and reliable operation of the flash memory mandates that the programming procedure be strictly followed.
One prior method of controlling the programming and erasure of flash memory requires rigid adherence to prevent overerasure. Overerasure typically is catastrophic to flash memories, as it typically results in the loss of the entire memory.
One prior method of controlling the programming and erasure of flash memory via a microprocessor requires a high degree of user sophistication to couple the microprocessor to the flash memory. Users of one prior method typically should be aware of the microprocessor's timing demands, as well as those of the flash memory. Users of the prior method typically should also monitor where in the programming or erase sequence the microprocessor is to prevent the possibility of issuing inappropriate commands to the memory at inappropriate points in a programming or erase sequence.